1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of an implanted bitline contact plug.
2) Description of the Prior Art
Advanced semiconductor chips, now being manufactured in industry, are composed of logic or memory devices. Logic devices are used to process information or data, while memory devices are used for data storage. These two types of devices can be found in almost all computers, however they are usually found on specific chips, reserved for either logic or memory applications. In systems in which logic and memory devices are packaged separately, data signals between the two may have to pass through several levels of packaging, which can result in undesirable propagation delays. In addition the manufacturing costs for fabricating wafers producing only logic chips, and wafers with only memory chips, are greater than if both logic and memory applications can be incorporated on the same chip. Therefore for performance and cost reasons the semiconductor industry has been motivated to produce a semiconductor chip with both the desired logic and memory requirements.
The state-of-the-art technologies for nonvolatile semiconductor memories are the SONOS (polysilicon-oxide-nitride-oxide-silicon) and the floating gate-type memories. The SONOS is a multi-gate dielectric device consisting of an oxide-nitride-oxide (ONO) layer in which charge storage takes place in discrete traps in the silicon nitride layer.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering Seong-Dong Kim, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 10, Oct. 2002 Advanced Source/Drain Engineering for Box-Shaped Ultrashallow Junction Formation Using Laser Annealing and Pre-Amorphization Implantation in Sub-100-nm SOI CMOS. http://www.ee.ucla.edu/faculty/papers/woo TransED oct02.pdf
U.S. Pat. No. 4,181,538 Narayan, et al. Jan. 1, 1980—shows a method for making defect-free zone by laser-annealing of doped silicon.
U.S. Pat. No. 6,465,306 Ramsbey, et al. Oct. 15, 2002—Simultaneous formation of charge storage and bitline to wordline isolation.
U.S. Pat. No. 6,500,713 Ramsbey et al.—shows a process for repairing damage to charge trapping dielectric layer from bit line implantation.
U.S. Pat. No. 6,110,845 Seguchi, et al. Aug. 29, 2000—Process for fabricating SOI substrate with high-efficiency recovery from damage due to Ion implantation.